2016全球异构计算HSA峰会

About the Summit

 As traditional homogeneous multi-core processor architectures gradually approach their physical limits, it is difficult to continue to improve chip performance, and excessive power consumption, area size and other issues follow. Heterogeneous computing, or so-called "big computing", is becoming an international mainstream technology. Based on heterogeneous computing technology, heterogeneous multi-core processors deeply integrate CPU, GPU, DSP, FPGA, ASIC and other fixed-function accelerators on the same chip to perform collaborating computing, storage and management. In terms of performance, power, and other key indicators, it has improved several times or even orders of magnitude more than existing homogeneous multi-core processors. In other words, the "CPU +" era has quietly emerged.

In the "CPU +" era, in addition to innovative technology, there are major issues we are facing including improving the relevant ecosystems, integrating the upstream and downstream industries, and opening up new markets, etc., which means the global industry community must work together.

HSAF (Heterogeneous System Architecture Foundation) is one of the most important non-profit international consortiums for the next generation of heterogeneous multi-core processors, bringing together a large number of processor-related hardware and software companies with significant influence, together to build and improve the HSA ecosystem.

The Heterogeneous System Architecture Foundation (HSAF) Heterogeneous Computing 2016 Global Summit is scheduled to be jointly hosted by HSAF and the China Semiconductor Industry Association (CSIA) on August 22 - 23 in the Beijing Economic and Technological Development Zone (E-Town), China, and this is the first time the HSAF Summit will be held in China. The Summit will examine integrated circuit technologies and its industry application and solutions. It will further consider the CPU + era and how to develop the next generation heterogeneous multi-core processors and other related systems.

The HSAF Heterogeneous Computing 2016 Global Summit anticipates invited leaders from the Cyberspace Administration of China, the Ministry of Industry and Information Technology, the Government of Beijing Municipality as well as industry experts will attend. In addition to HSAF members, multiple influential industry/academia/research institutes, SoC IP vendors, processor design companies, tools vendors, OSVs and ISVs are confirmed to attend, including Huawei, the Chinese Academy of Sciences (CAS), Peking University, etc. 

 

5 Reasons to Participate in the HSA Summit:

The Heterogeneous multi-core processor software programming threshold is greatly reduced, and the unified programming, debugging and optimizations based on different types of processor cores and accelerated circuit units is fully realized.

1 Simplified chip architecture design
1 Significantly improved chip performance
1 Widely shared software ecosystem
1 Shortened project development cycle
1 Lowered application programming threshold

Summit Agenda

Beijing August 22 Beijing August 23
  • August 22, 2016

    Morning (9:00 AM – 12:00 PM)
    Moderator: Liang, Sheng (Director of Administrative Committee of Beijing Economic and Technological Development Zone – E-Town)
    Time Topics Speaker Position
    9:00-9:05 Administrative Committee of Beijing Economic and Technological Development Zone - E Town Liang, Sheng Director
    9:05-9:20 Address – Cyberspace Administration of China Zhuang, Rongwen Deputy Director
    9:20-9:25 Address – Ministry of Industry and Information Technology of the People's Republic of China
    9:25-9:35 Embracing the trends of heterogeneous computing development Ni, Guangnan Academician of Chinese Academy of Engineering (CAE)
    9:35-9:50 Thoughts on China’s processor development Zhou, Hongren Executive Deputy Director of the Advisory Committee for State Informatization (ACSI)
    9:50-10:10 Coffee Break
    10:10-10:30 China's IC industry development and trends Xu, Xiaotian Executive Deputy Director of CSIA
    10:30-10:55 HSA Foundation recent progress and prospects Dr. Glossner, John President of HSA Foundation
    10:55-11:15 Heterogeneous multi-core chip solution Lee, Allen AMD Corporate Vice President of Engineering and General Manager of China R&D Center at AMD
    11:15-11:35 Heterogeneous multi-core chip solution Li, Keyi Chief Executive Officer of Huaxia General Processor Technologies
    11:35-11:55 Heterogeneous multi-core chip solution Dr. Ju, Roy Senior Technical Director and SW Architect of MediaTek, Member of Board of Directors for the HSA Foundation, Chair for multivendor working group at the HSA Foundation
    11:55-12:15 Heterogeneous multi-core chip solution Liu, James Vice President and General Manager China at Imagination Technologies
    August 22, 2016 Afternoon (14: 00pm – 17: 00pm)
    Forum: Heterogeneous Computing Processor Design, Tools and Manufacturing
    Moderator: Dr. Ju, Roy
    Time Topics Speaker
    14:00-14:20 Research on high-performance server chips based on heterogeneous computing Shenwei
    14:20-14:40 Heterogeneous multi-core system architecture research MPRC PKUnity
    14:40-15:00 Heterogeneous system architecture, tools and its standardized development HSA Foundation
    15:00-15:20 Computer vision solutions based on heterogeneous multi-cores Synopsys
    15:20-15:40 Heterogeneous system architecture challenges for chip design and verification Cadence
    15:40-16:00 Semiconductor technology development trends and design challenges for next-generation SoC GUC
    16:00-16:20 Demand and Practice for HSA SoC in China Market Qualchip Technologies
    16:20-16:50 Press Release / Demo MediaTek,Huaxia General Processor Technologies, Imagination Technologies, CEVA
    16:50-17:20 Attendees Q&A Session HSA Foundation
  • August 23, 2016

    August 23, 2016 Morning (9: 30am – 12: 00pm)
    Forum: Heterogeneous Computing Applications
    Moderator: Xiong, Wen Imagination Technologies – Manager North China
    Time Topics Speaker
    9:30-9:50 High-performance chip in cloud computing and big data applications CAS Institute of Computing Technology
    9:50-10:10 Power system control and high-performance computing State Grid
    10:10-10:30 Research on the next-generation software defined radio based on heterogeneous computing National University of Defense Technology
    10:30-10:50 Research on heterogeneous computing in high-precision satellite navigation and positioning Shanghai Jiao Tong University
    10:50-11:00 Coffee Break
    11:00-11:20 Integration of SyberOS mobile security solutions and domestic chips SyberOS
    11:20-11:40 Heterogeneous computing and chip solution based on many-core architecture Sun Yat-sen University
    11:40-12:00 Heterogeneous computing applications in multi-mode baseband chips Jiangsu Software Defined Radio Engineering Research Center
    12:00-12:20 Exploration of heterogeneous computing applications in AR/VR AMD
    Afternoon (14:00 PM – 16:30 PM)
    Forum: Heterogeneous Computing Processor Applications and Solutions
    Moderator: Chu, Hanjin  Director of AMD China VR, Compute Platform and Solutions
    Time Topics Speaker
    14:00-14:20 Task parallel Programming Model LG
    14:20-14:35 Exploration of 5G demand for high-performance computing chips Shanghai Research Center of Wireless Communication
    14:35-14:55 Exploration of 5G demand for high-performance computing chips Shanghai Research Center of Wireless Communication
    14:55-15:15 Research on potential open source video libraries for HSA Hunan University of Science and Technology
    15:15-15:25 Coffee Break
    15:25-15:45 Research on the trends of the next-generation intelligent unmanned aerial vehicles Hiwing Aviation General Equipment
    15:45-16:05 Tensor computing, artificial intelligence and deep learning CEVA
    16:05-16:25 Development and trends of broadband power line carrier communication and its application Sigbean Broadband PLC Communications
    16:25-16:45 Analysis of Internet of Things trends and its software / hardware ecosystem Anhui Baolong

Guest Info

Guangnan Ni

Academician of the Chinese Academy of Engineering

Guangnan Ni is one of the first academicians of the Chinese Academy of Engineering. He received the Lifetime Achievement Award from Chinese Information Processing Society of China and China Computer Federation in 2011 and 2015 respectively. He is committed to the development of China's information core technology and industry and is highly influential in hardware and software system's policymaking and standards in China.

Hongren Zhou

Researcher and PhD supervisor, Executive Deputy Director of the Advisory Committee for State Informatization (ACSI)

Dr. Hongren Zhou, researcher and PhD supervisor, was former senior advisor to the United Nations Department of Economic and Social Affairs. Dr. Zhou now serves as Executive Deputy Director of the Advisory Committee for State Informatization (ACSI) responsible for the construction and management of national economic information systems.

Xiaotian Xu

Executive Deputy Director of CSIA

Xiaotian Xu is Executive Deputy Director of China Semiconductor Industry Association (CSIA), he served in No. 24 Research Institute of CETC and China National Electronic Devices Corp. Mr. Xu was Director of Executive Office at the Department of Electronics Microelectronics Bureau, Director of the Microelectronics and Products Division at the Department of Mechanical and Electronics, Director of General Products Division at the Department of Electronics and Director of Electronic Information Products Division and Assistant Counsel at the Ministry of information and industry.

John Glossner

President of the HSA Foundation

Dr. John Glossner is President of the HSA Foundation and CEO of Optimum Semiconductor Technologies, Inc. dba General Processor Technologies, the US division of China-based Wuxi DSP. Prior to joining Wuxi DSP, Dr. Glossner co-founded Sandbridge Technologies and served as EVP & CTO. Prior to Sandbridge, he managed both technical and business activities in DSP and Broadband Communications at IBM and Lucent/Motorola’s Starcore. He is also an associate professor at Daniel Webster College and chairs the department of Computer Science. Dr. Glossner received his Ph.D. in Electrical Engineering from TU Delft in the Netherlands, M.S. degrees in E.E. and Eng. Mgt. from NTU, and holds a B.S.E.E. degree from Penn State. John has more than 120 publications and 36 issued patents.

Allen Lee

Corporate Vice President of Engineering at AMD

Allen Lee Corporate Vice President of Engineering GM, China R&D Center Allen Lee has over 27 years experience in semiconductor industry currently serves as Corporate Vice President of Engineering at AMD. Allen is responsible for the establishment of Engineering R&D organization in China for AMD. Allen joined AMD through its acquisition of ATI Technologies Inc. at Oct. 2006, prior to AMD Allen was VP of Engineering for Integrated Graphics Business Unit at ATI from 2002 to 2006 responsible for the development of ATI Chipsets products. Prior to joining ATI in 2002, he spent 10 years at S3 Inc., Last position Allen hold at S3 was Sr. Director of hardware engineering responsible for Graphics products development. Allen also held manager position at SMOS, a Seiko Epson affiliate in US. Allen Lee received MS degree in Electrical Engineering from University of Missouri at Columbia.

Kerry Li

Founder and Chair of the Board of Huaxia General Processor

Kerry Li is founder and Chair of the Board of Huaxia General Processor Technologies. In 2015, Mr. Li was elected to "Innovative Talent Promotion Plan" by China's Ministry of Science & Technology and China's 1000 Talents. Mr. Li received his M.S. degree in Electrical Engineering from Wayne State University and his M.B.A. from University of Chicago.

Greg Stoner

Director of the Radeon Open Compute Initiative in AMD’s Radeon Technology Group

Greg Stoner is Sr. Director of the Radeon Open Compute Initiative in AMD’s Radeon Technology Group, Board Director for the OpenACC Group, Managing Dir. and Chairman of the Board for the HSA Foundation, and is a permanent member of the OpenMP Architecture Review Board. Stoner is responsible for AMD’s GPU Compute Strategy and Roadmap and leads the Radeon Open Compute Engineering team. Stoner has a strong professional background in the computing industry with over 20 years of experience in hardware and application development. Stoner was also a Dir. of Business Development in the Visual Computing Software Group at Intel, and held positions previously at Motorola, Ageia Technologies, Digital Domain, Metrowerks (A Motorola company), and at MIPS Technology. Stoner did advanced studies in business at Stanford University and with undergraduate studies in Material Science and Engineering at the University of Michigan.

Roy Ju

Sr. Technical Director and SW Architect at MediaTek

Roy Ju is Sr. Technical Director and SW Architect at MediaTek and is driving the heterogeneous computing and compiler optimization solutions on MediaTek mobile platforms. He serves as an expert of the HSA Foundation and runs the multivendor working group. He is also involved in SW strategy and other technology initiatives at Corporate Technology Office. Dr. Ju has had more than 20 years of industrial experiences on technology and product developments in the areas of programming systems, compiler optimizations, parallel processing, and processor architecture and has held various technical and management positions at AMD, Google, Intel, HP, and IBM. Prior to joining MediaTek in 2013, Dr. Ju was a Sr. Fellow and the compiler architect of the Heterogeneous System Architecture (HSA) project at AMD. During 1999 through 2005 at Intel, Dr. Ju spearheaded an Itanium Open Research Compiler, which was in collaboration with the Institute of Computing Technology at Chinese Academy of Sciences and released to the open source research community worldwide. Dr. Ju received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in Electrical and Computer Engineering from University of Texas at Austin.

James Liu

Vice President and General Manager China at Imagination Technologies

James Liu is Vice President and General Manager China for Imagination Technologies. Mr. Liu brings to Imagination 20+ years of experience in the China electronics design industry. Prior to joining Imagination in 2015, Mr. Liu spent 18 years at Cadence Design Systems, where he most recently held the role of China site manager – managing 700 employees across multiple sites – and VP of worldwide field operations for China, leading an organization of around 100 people. During his time at Cadence, he held positions in many key customer-facing roles including FAE, product specialist, sales manager, regional GM and national sales director. Prior to joining Cadence, Mr. Liu worked in a government institute as an R&D engineer/project manager for seven years. He holds an MSEE and an EMBA.

Mr. LU Junlin

deputy director of Computer Architecture Institute in Peking University

Mr. LU Junlin was born in China, on January 8, 1980. He received his bachelor and Ph.D degrees in Computer Science from Peking University respectively. He is the deputy director of Computer Architecture Institute in Peking University. Lu’s research focus on computer architecture, system-on-chip and software/hardware co-design. He is a lecturer of several fundamental courses in Peking University and gets many teaching excellence awards. Lu is also a member of the CE2016 Steering Committee in ACM, participating in writing “Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering”.

Yin luo sheng

Synopsys Asia Pacific processor product solutions manager.

Master of automatic control theory and engineering, Synopsys Asia Pacific processor product solution manager.

Mao Liu

Mao Liu has been working in the semiconductor industry for over 16 years. Mao currently works for Cadence as Technical Marketing Director and technical assistant of Cadence APAC President. Prior to joining Cadence

Mao Liu has been working in the semiconductor industry for over 16 years. Mao currently works for Cadence as Technical Marketing Director and technical assistant of Cadence APAC President. Prior to joining Cadence, Mao was BU head in O2 Micro, Director of Marketing of Telegent, a startup acquired by Spreadtrum and Senior Product Marketing Manager at Sirf/CSR. Mao is the inventor of 5 issued US patents. He holds EE degree from Shanghai Jiaotong University and started as ASIC design and verification engineer in the beginning of his career. 

Louis Lin

Vice President of Design Service at GUC

Louis Lin received the M.S. and Ph.D. degrees both in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1993 and 1998, respectively. His research interests include low power design, power estimation, and testing. In 1998, he joined Global Unichip Corporation (GUC), a company providing SoC design services to worldwide customers. His job experiences include design flow development, low power design, and SoC chip implementation service, etc. He is currently serving as Vice President of Design Service at GUC, and responsible for all chip implementations and project managements. He has led teams at GUC to successfully complete over 500 tapeouts.

Jianyu Gu

President of Qualchip Technologies

Jianyu Gu, President of Qualchip Technologies Mr. Gu has become President of Qualchip Technologies since 2009. He worked in US between 1995-2006 as a Senior Engineer at Samsung Semiconductors, Principal Engineer at Cadence Design Systems, ASIC Director at Hifn, and Senior ASIC Director at Legend Silicon Corp (2006-2009). After the graduation from Sun Yat-Sen University in Guangzhou in 1982, Mr. Gu worked at Beijing Dongguang Semiconductors Corp. (No.878 Factory). Since then, Mr. Gu has contributed his distinguished accomplishments in the field of IC design. He was responsible for the work of Design Center at Dongguang for a long time, and he also served as one of the Chief Designers at Beijing IC Design Center (BIDC) for several years. For over three decades, Mr. Gu had directed, managed and independently designed hundreds of IC projects, all of which have achieved first silicon successes.

Yaozhong Xin

National University of Defense Technology

Dr. Yaozhong Xin is a Professional Senior Engineer, former deputy director of the National Electric Power Dispatching and Control Center of State Grid Corporation of China(SGCC), the Secretary-general of Chinese National standards committee of Power Grid operation and Control (SAC/TC446), the Vice Chairman of Chinese National standards committee of Power System Management and Associated Information exchange (SAC/TC82), a member of IEC TC57 WG13 and WG19, senior member of IEEE, the Chairman of Smart Grid Committee and member of Governor Board of the GO15 (International Power Grid Operators).

Rongchun Li

Shanghai Jiao Tong University

Rongchun Li, men, was born in China, May 21th, 1985. Now he is an assistant professor at National Laboratory for Parallel and Distributed Processing, School of Computer, National University of Defense Technology, Changsha, China. He received the B.S. in Computer Science and Technology from Wuhan University, Wuhan, China, in 2007, and M.S. and Ph.D. in Computer Science and Technology from National University of Defense Technology, Changsha, China, in 2009 and 2014, respectively. His research focuses on the heterogeneous high-performance computing and software defined radio (SDR). He is familiar with common heterogeneous platforms, such as FPGA, GPU, MIC. In recently years, he mainly studies the GPU-based SDR system and proposed the CuSora, a GPU-based SDR system based on Sora. He also implemented many baseband modules, such as the FEC encoder and decoder, OFDM demodulator, MIMO detector on the GPU platform. He published 18 papers in the international conference or journal, including IEEE Transactions on Circuits and Systems, Journal of System Architecture, WCNC, etc. Among these, there are 13 papers indexed in SCI, 5 papers index in EI.

Xin Chen

Sun Yat-sen University

Xin Chen received his B.S. and M.S. in electronics engineering from Southeast University in China and his Ph.D. in electronics and telecommunication engineering from Politecnico di Torino in Italy. In 2011,he was a visiting Research at the University of Miami, USA Currently, he is an assistant professor in the School of Electronic Information and Electrical Engineering at Shanghai Jiao Tong University. His current research interests focus on GNSS receiver multipath mitigation, interference suppression, and multipath channel modeling. For the first time in the world, He proposed the life-time model of multipath signals from different satellite orbits. Multipath mitigation algorithms was also proposed to improve positioning accuracy in the urban environment. He has published a book in English, five papers published in SCI, nine papers published in EI. He currently serves as a member of the ION SDR Metadata Standard Committee.

Zhiyi Yu

SyberOS

Zhiyi Yu is a Tenure-track associate professor of SYSU-CMU Joint Institute of Engineering, and a full professor of school of electronics and information engineering, Sun Yat-sen University, and an adjunct professor of ECE department of Carnegie Mellon University, USA. He was with IntellaSys Corporation, USA, and the State Key Laboratory of ASIC & System, Fudan University, China. Dr. Yu received the B.S. and M.S. degrees in EE from Fudan University, China, and the Ph.D. degree in ECE from the University of California, Davis. His research interests include VLSI design and computer architecture. Recent projects include the many-core processors with efficient inter-core communications and heterogeneous accelerators. He designed over 10 chips including the 16-core, 24-core 64-core, and 2.5D multi-chip system. He has published over 90 papers, including 3 at the IEEE International Solid-State Circuits Conference (ISSCC) and 15 in IEEE Transactions/Journals. He is an IEEE Senior Member, serves in the editorial board of Journal of Semiconductors in China, and have served on the Technical Program Committees of many conferences such as IEEE ASSCC, IFIP/IEEE VLSI-SOC, IEEE/ACM ISLPED, ACM MES, APSIPA, SASIMI, NoCArc, and ASICON.

Zhao Chunlei

Jiangsu Software Defined Radio Engineering Research Center

Zhao Chunlei, Vice President&CTO, Beijing Yuanxin Technology Co.,LTD. As an expert in mobile OS, Chunlei has years of research and product experience in Linux,Vxworks and Android. He had taken the job of senior technology management in lots of famous company such as Trolltech and Lenovo, and acted as the chief architect of Linux phone and 1st LePhone in Lenovo. In recent years, He established the SyberOS R&D team, and released the SyberOS security solution, which has a big influence in the information Industry in China.

XiaodongZhang

AMD

Xiaodong Zhang got his PhD degree from Southeast University, China in 2001. He joined Chinese Academy of Science (CAS) after he had finished his post-doc research at Nanjing Automation Research Institute in 2004. From the late of 2007 to the late of 2011, he joined ShanghaiSpreadtrum for the research of LTE formerly and soonextended to the design and verification of 2G/3G/LTE baseband chips, where he worked as a System Designdirector.  At the early of 2012, he was invited back towork in CAS, where he focused on broadband wireless communications as well as domain specific-signal processor designs. In the middle of 2015, he left CAS for the second time and joined the current company he is now serving, GPT/HX, working as a strategy director. Meanwhile Dr Zhang is also very interested in the latest achievements made on the convergence of any traditionally separate-area processors, e.g. CPU, GPU and DSP, using the methodology delivered by the HSA foundation (www.hsafoundation.com). Furthermore, it is strongly believed by him that rather than simply integrating the current separate processors together, a much more efficient, powerful and unified design should be more appropriate for the CPU+ era that would accommodate the different requirements from different application areas.

Hanjin Chu

AMD

Director of AMD China VR, Compute Platform and Solutions. He is responsible for leading Applications & Solutions cooperation with partners in VR, Gaming, Heterogeneous Computing. Hanjin Chu used to work in Motorola, WindRiver Systems Ltd. Hanjin graduated at 1998 with Master Degree in HeFei University of Technology.

Jaewon Kim

Shanghai Research Center of Wireless Communication

Jaewon Kim SoC Architect at SIC center, LG Electronics Jaewon Kim is Chief SoC Architect at MSoC Division, SIC Center of LG Electronics and represents LG Electronics in the Board for the HSA Foundation. He is responsible for System Architecture and Specifications for Mobile Application Processors in LG. Dr. Kim has had 20 years of strong experiences on computer HW architecture, SW development and System-on-Chip development through semiconductor and VLSI CAD companies, Qualcomm Inc., nVidia and Synopsys. He received his Ph.D. in Computer Science from University of Illinois at Urbana-Champagne.

Yang Yang

Hunan University of Science and Technology

Yang Yang received the BEng and MEng degrees in Radio Engineering from Southeast University, Nanjing, P. R. China, in 1996 and 1999, respectively; and the PhD degree in Information Engineering from The Chinese University of Hong Kong in 2002.  Dr. Yang Yang is currently a professor with Shanghai Institute of Microsystem and Information Technology (SIMIT), Chinese Academy of Sciences, serving as the Director of CAS Key Laboratory of Wireless Sensor Network and Communication, and the Director of Shanghai Research Center for Wireless Communications (WiCO). He is also an adjunct professor with the School of Information Science and Technology, ShanghaiTech University. Prior to that, he has served the Department of Electronic and Electrical Engineering at University College London (UCL), United Kingdom, as a Senior Lecturer; the Department of Electronic and Computer Engineering at Brunel University, United Kingdom, as a Lecturer; and the Department of Information Engineering at The Chinese University of Hong Kong as an Assistant Professor. His research interests include wireless ad hoc and sensor networks, software defined wireless networks, 5G mobile systems, intelligent transport systems, wireless testbed development and practical experiments.  Dr. Yang Yang has co-edited a book on heterogeneous cellular networks (2013, Cambridge University Press) and co-authored more than 100 technical papers. He has been serving in the organization teams of about 50 international conferences, e.g. a co-chair of Ad-hoc and Sensor Networking Symposium at IEEE ICC’15, a co-chair of Communication and Information System Security Symposium at IEEE Globecom’15.

Guosong Zhang

Hunan University of Science and Technology

Guosong Zhang, Male, Born in 1979/12/22, Chinese nationality,Founder and general manager of Beijing SigBean Information Technology Co. Ltd. He graduated from Beijing University of Posts and Telecommunications in 2006, with master’s degree of communication and information system. After graduation in 2006, Guosong Zhang has been engaged in research and design of mobile communication terminal baseband chips, and worked for Fujitsu China R&D center and Apacewave, a US. high tech. company. 2010 as a start-up participate in the establishment of Xincomm communication Co. Ltd, he successfully developed FDD/TDD LTE 4G dual mode terminal baseband chip. In 2015, he founded Beijing SigBean Information Technology Co. Ltd., and focus on research and development of broadband PLC SOC. As the first inventor, he has submitted 14 patents.

HSA related

HSA Summary

The HSA (Heterogeneous System Architecture) Foundation is a non-profit consortium of SoC IP vendors, OEMs, Academia, SoC vendors, OSVs and ISVs, whose goal is making programming for parallel computing easy and pervasive. HSA members are building a heterogeneous computing ecosystem, rooted in industry standards, which combines scalar processing on the CPU with parallel processing on kernel agents including GPU, DSP, and other accelerators. This enables high bandwidth access to memory and high application performance with low power consumption. HSA defines interfaces for parallel computation using CPU, GPU, DSP, FPGA and other programmable and fixed function devices, while supporting a diverse set of high-level programming languages, and creating the foundation for next-generation, general-purpose computing.


HSA Heterogeneous Computing

Based on heterogeneous computing technology, the heterogeneous multi-core processor deeply integrates CPU, GPU, DSP, FPGA, ASIC and other different types of processor cores and on the same chip for collaborative computing, storage and management in accordance with consistent hardware / software interface standards and specifications.


Goal of the Heterogeneous Computing

Compared with the prior homogeneous multicore processors and the same type of SoC chips, heterogeneous multi-core processors have significantly improved performance by up to orders of magnitude in terms of performance, power and other key indicators.


HSA Members

http://www.hsafoundation.com/members/


Venue Info

Fengda International Hotel
No. 20 Ronghua Middle Road (Intersection of Ronghua Middle Road and Zhonghe Street) Daxing Economic Development Zone, Beijing, China