As traditional homogeneous multi-core processor architectures gradually approach their physical limits, it is difficult to continue to improve chip performance, and excessive power consumption, area size and other issues follow. Heterogeneous computing, or so-called "big computing", is becoming an international mainstream technology. Based on heterogeneous computing technology, heterogeneous multi-core processors deeply integrate CPU, GPU, DSP, FPGA, ASIC and other fixed-function accelerators on the same chip to perform collaborating computing, storage and management. In terms of performance, power, and other key indicators, it has improved several times or even orders of magnitude more than existing homogeneous multi-core processors. In other words, the "CPU +" era has quietly emerged.
In the "CPU +" era, in addition to innovative technology, there are major issues we are facing including improving the relevant ecosystems, integrating the upstream and downstream industries, and opening up new markets, etc., which means the global industry community must work together.
HSAF (Heterogeneous System Architecture Foundation) is one of the most important non-profit international consortiums for the next generation of heterogeneous multi-core processors, bringing together a large number of processor-related hardware and software companies with significant influence, together to build and improve the HSA ecosystem.
The Heterogeneous System Architecture Foundation (HSAF) Heterogeneous Computing 2016 Global Summit is scheduled to be jointly hosted by HSAF and the China Semiconductor Industry Association (CSIA) on August 22 - 23 in the Beijing Economic and Technological Development Zone (E-Town), China, and this is the first time the HSAF Summit will be held in China. The Summit will examine integrated circuit technologies and its industry application and solutions. It will further consider the CPU + era and how to develop the next generation heterogeneous multi-core processors and other related systems.
The HSAF Heterogeneous Computing 2016 Global Summit anticipates invited leaders from the Cyberspace Administration of China, the Ministry of Industry and Information Technology, the Government of Beijing Municipality as well as industry experts will attend. In addition to HSAF members, multiple influential industry/academia/research institutes, SoC IP vendors, processor design companies, tools vendors, OSVs and ISVs are confirmed to attend, including Huawei, the Chinese Academy of Sciences (CAS), Peking University, etc.
The Heterogeneous multi-core processor software programming threshold is greatly reduced, and the unified programming, debugging and optimizations based on different types of processor cores and accelerated circuit units is fully realized.
|Morning (9:00 AM – 12:00 PM)|
|Moderator: Liang, Sheng (Director of Administrative Committee of Beijing Economic and Technological Development Zone – E-Town)|
|9:00-9:05||Administrative Committee of Beijing Economic and Technological Development Zone - E Town||Liang, Sheng||Director|
|9:05-9:20||Address – Cyberspace Administration of China||Zhuang, Rongwen||Deputy Director|
|9:20-9:25||Address – Ministry of Industry and Information Technology of the People's Republic of China|
|9:25-9:35||Embracing the trends of heterogeneous computing development||Ni, Guangnan||Academician of Chinese Academy of Engineering (CAE)|
|9:35-9:50||Thoughts on China’s processor development||Zhou, Hongren||Executive Deputy Director of the Advisory Committee for State Informatization (ACSI)|
|10:10-10:30||China's IC industry development and trends||Xu, Xiaotian||Executive Deputy Director of CSIA|
|10:30-10:55||HSA Foundation recent progress and prospects||Dr. Glossner, John||President of HSA Foundation|
|10:55-11:15||Heterogeneous multi-core chip solution||Lee, Allen||AMD Corporate Vice President of Engineering and General Manager of China R&D Center at AMD|
|11:15-11:35||Heterogeneous multi-core chip solution||Li, Keyi||Chief Executive Officer of Huaxia General Processor Technologies|
|11:35-11:55||Heterogeneous multi-core chip solution||Dr. Ju, Roy||Senior Technical Director and SW Architect of MediaTek, Member of Board of Directors for the HSA Foundation, Chair for multivendor working group at the HSA Foundation|
|11:55-12:15||Heterogeneous multi-core chip solution||Liu, James||Vice President and General Manager China at Imagination Technologies|
|August 22, 2016 Afternoon (14: 00pm – 17: 00pm)|
|Forum: Heterogeneous Computing Processor Design, Tools and Manufacturing|
|Moderator: Dr. Ju, Roy|
|14:00-14:20||Research on high-performance server chips based on heterogeneous computing||Shenwei|
|14:20-14:40||Heterogeneous multi-core system architecture research||MPRC PKUnity|
|14:40-15:00||Heterogeneous system architecture, tools and its standardized development||HSA Foundation|
|15:00-15:20||Computer vision solutions based on heterogeneous multi-cores||Synopsys|
|15:20-15:40||Heterogeneous system architecture challenges for chip design and verification||Cadence|
|15:40-16:00||Semiconductor technology development trends and design challenges for next-generation SoC||GUC|
|16:00-16:20||Demand and Practice for HSA SoC in China Market||Qualchip Technologies|
|16:20-16:50||Press Release / Demo||MediaTek,Huaxia General Processor Technologies, Imagination Technologies, CEVA|
|16:50-17:20||Attendees Q&A Session||HSA Foundation|
|August 23, 2016 Morning (9: 30am – 12: 00pm)|
|Forum: Heterogeneous Computing Applications|
|Moderator: Xiong, Wen Imagination Technologies – Manager North China|
|9:30-9:50||High-performance chip in cloud computing and big data applications||CAS Institute of Computing Technology|
|9:50-10:10||Power system control and high-performance computing||State Grid|
|10:10-10:30||Research on the next-generation software defined radio based on heterogeneous computing||National University of Defense Technology|
|10:30-10:50||Research on heterogeneous computing in high-precision satellite navigation and positioning||Shanghai Jiao Tong University|
|11:00-11:20||Integration of SyberOS mobile security solutions and domestic chips||SyberOS|
|11:20-11:40||Heterogeneous computing and chip solution based on many-core architecture||Sun Yat-sen University|
|11:40-12:00||Heterogeneous computing applications in multi-mode baseband chips||Jiangsu Software Defined Radio Engineering Research Center|
|12:00-12:20||Exploration of heterogeneous computing applications in AR/VR||AMD|
|Afternoon (14:00 PM – 16:30 PM)|
|Forum: Heterogeneous Computing Processor Applications and Solutions|
|Moderator: Chu, Hanjin Director of AMD China VR, Compute Platform and Solutions|
|14:00-14:20||Task parallel Programming Model||LG|
|14:20-14:35||Exploration of 5G demand for high-performance computing chips||Shanghai Research Center of Wireless Communication|
|14:35-14:55||Exploration of 5G demand for high-performance computing chips||Shanghai Research Center of Wireless Communication|
|14:55-15:15||Research on potential open source video libraries for HSA||Hunan University of Science and Technology|
|15:25-15:45||Research on the trends of the next-generation intelligent unmanned aerial vehicles||Hiwing Aviation General Equipment|
|15:45-16:05||Tensor computing, artificial intelligence and deep learning||CEVA|
|16:05-16:25||Development and trends of broadband power line carrier communication and its application||Sigbean Broadband PLC Communications|
|16:25-16:45||Analysis of Internet of Things trends and its software / hardware ecosystem||Anhui Baolong|
Guangnan Ni is one of the first academicians of the Chinese Academy of Engineering. He received the Lifetime Achievement Award from Chinese Information Processing Society of China and China Computer Federation in 2011 and 2015 respectively. He is committed to the development of China's information core technology and industry and is highly influential in hardware and software system's policymaking and standards in China.
Dr. Hongren Zhou, researcher and PhD supervisor, was former senior advisor to the United Nations Department of Economic and Social Affairs. Dr. Zhou now serves as Executive Deputy Director of the Advisory Committee for State Informatization (ACSI) responsible for the construction and management of national economic information systems.
Xiaotian Xu is Executive Deputy Director of China Semiconductor Industry Association (CSIA), he served in No. 24 Research Institute of CETC and China National Electronic Devices Corp. Mr. Xu was Director of Executive Office at the Department of Electronics Microelectronics Bureau, Director of the Microelectronics and Products Division at the Department of Mechanical and Electronics, Director of General Products Division at the Department of Electronics and Director of Electronic Information Products Division and Assistant Counsel at the Ministry of information and industry.
Dr. John Glossner is President of the HSA Foundation and CEO of Optimum Semiconductor Technologies, Inc. dba General Processor Technologies, the US division of China-based Wuxi DSP. Prior to joining Wuxi DSP, Dr. Glossner co-founded Sandbridge Technologies and served as EVP & CTO. Prior to Sandbridge, he managed both technical and business activities in DSP and Broadband Communications at IBM and Lucent/Motorola’s Starcore. He is also an associate professor at Daniel Webster College and chairs the department of Computer Science. Dr. Glossner received his Ph.D. in Electrical Engineering from TU Delft in the Netherlands, M.S. degrees in E.E. and Eng. Mgt. from NTU, and holds a B.S.E.E. degree from Penn State. John has more than 120 publications and 36 issued patents.
Allen Lee Corporate Vice President of Engineering GM, China R&D Center Allen Lee has over 27 years experience in semiconductor industry currently serves as Corporate Vice President of Engineering at AMD. Allen is responsible for the establishment of Engineering R&D organization in China for AMD. Allen joined AMD through its acquisition of ATI Technologies Inc. at Oct. 2006, prior to AMD Allen was VP of Engineering for Integrated Graphics Business Unit at ATI from 2002 to 2006 responsible for the development of ATI Chipsets products. Prior to joining ATI in 2002, he spent 10 years at S3 Inc., Last position Allen hold at S3 was Sr. Director of hardware engineering responsible for Graphics products development. Allen also held manager position at SMOS, a Seiko Epson affiliate in US. Allen Lee received MS degree in Electrical Engineering from University of Missouri at Columbia.
Kerry Li is founder and Chair of the Board of Huaxia General Processor Technologies. In 2015, Mr. Li was elected to "Innovative Talent Promotion Plan" by China's Ministry of Science & Technology and China's 1000 Talents. Mr. Li received his M.S. degree in Electrical Engineering from Wayne State University and his M.B.A. from University of Chicago.
Greg Stoner is Sr. Director of the Radeon Open Compute Initiative in AMD’s Radeon Technology Group, Board Director for the OpenACC Group, Managing Dir. and Chairman of the Board for the HSA Foundation, and is a permanent member of the OpenMP Architecture Review Board. Stoner is responsible for AMD’s GPU Compute Strategy and Roadmap and leads the Radeon Open Compute Engineering team. Stoner has a strong professional background in the computing industry with over 20 years of experience in hardware and application development. Stoner was also a Dir. of Business Development in the Visual Computing Software Group at Intel, and held positions previously at Motorola, Ageia Technologies, Digital Domain, Metrowerks (A Motorola company), and at MIPS Technology. Stoner did advanced studies in business at Stanford University and with undergraduate studies in Material Science and Engineering at the University of Michigan.
Roy Ju is Sr. Technical Director and SW Architect at MediaTek and is driving the heterogeneous computing and compiler optimization solutions on MediaTek mobile platforms. He serves as an expert of the HSA Foundation and runs the multivendor working group. He is also involved in SW strategy and other technology initiatives at Corporate Technology Office. Dr. Ju has had more than 20 years of industrial experiences on technology and product developments in the areas of programming systems, compiler optimizations, parallel processing, and processor architecture and has held various technical and management positions at AMD, Google, Intel, HP, and IBM. Prior to joining MediaTek in 2013, Dr. Ju was a Sr. Fellow and the compiler architect of the Heterogeneous System Architecture (HSA) project at AMD. During 1999 through 2005 at Intel, Dr. Ju spearheaded an Itanium Open Research Compiler, which was in collaboration with the Institute of Computing Technology at Chinese Academy of Sciences and released to the open source research community worldwide. Dr. Ju received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in Electrical and Computer Engineering from University of Texas at Austin.
James Liu is Vice President and General Manager China for Imagination Technologies. Mr. Liu brings to Imagination 20+ years of experience in the China electronics design industry. Prior to joining Imagination in 2015, Mr. Liu spent 18 years at Cadence Design Systems, where he most recently held the role of China site manager – managing 700 employees across multiple sites – and VP of worldwide field operations for China, leading an organization of around 100 people. During his time at Cadence, he held positions in many key customer-facing roles including FAE, product specialist, sales manager, regional GM and national sales director. Prior to joining Cadence, Mr. Liu worked in a government institute as an R&D engineer/project manager for seven years. He holds an MSEE and an EMBA.
Mr. LU Junlin was born in China, on January 8, 1980. He received his bachelor and Ph.D degrees in Computer Science from Peking University respectively. He is the deputy director of Computer Architecture Institute in Peking University. Lu’s research focus on computer architecture, system-on-chip and software/hardware co-design. He is a lecturer of several fundamental courses in Peking University and gets many teaching excellence awards. Lu is also a member of the CE2016 Steering Committee in ACM， participating in writing “Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering”.
Master of automatic control theory and engineering, Synopsys Asia Pacific processor product solution manager.
Mao Liu has been working in the semiconductor industry for over 16 years. Mao currently works for Cadence as Technical Marketing Director and technical assistant of Cadence APAC President. Prior to joining Cadence, Mao was BU head in O2 Micro, Director of Marketing of Telegent, a startup acquired by Spreadtrum and Senior Product Marketing Manager at Sirf/CSR. Mao is the inventor of 5 issued US patents. He holds EE degree from Shanghai Jiaotong University and started as ASIC design and verification engineer in the beginning of his career.
Louis Lin received the M.S. and Ph.D. degrees both in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1993 and 1998, respectively. His research interests include low power design, power estimation, and testing. In 1998, he joined Global Unichip Corporation (GUC), a company providing SoC design services to worldwide customers. His job experiences include design flow development, low power design, and SoC chip implementation service, etc. He is currently serving as Vice President of Design Service at GUC, and responsible for all chip implementations and project managements. He has led teams at GUC to successfully complete over 500 tapeouts.
Jianyu Gu, President of Qualchip Technologies Mr. Gu has become President of Qualchip Technologies since 2009. He worked in US between 1995-2006 as a Senior Engineer at Samsung Semiconductors, Principal Engineer at Cadence Design Systems, ASIC Director at Hifn, and Senior ASIC Director at Legend Silicon Corp (2006-2009). After the graduation from Sun Yat-Sen University in Guangzhou in 1982, Mr. Gu worked at Beijing Dongguang Semiconductors Corp. (No.878 Factory). Since then, Mr. Gu has contributed his distinguished accomplishments in the field of IC design. He was responsible for the work of Design Center at Dongguang for a long time, and he also served as one of the Chief Designers at Beijing IC Design Center (BIDC) for several years. For over three decades, Mr. Gu had directed, managed and independently designed hundreds of IC projects, all of which have achieved first silicon successes.
The HSA (Heterogeneous System Architecture) Foundation is a non-profit consortium of SoC IP vendors, OEMs, Academia, SoC vendors, OSVs and ISVs, whose goal is making programming for parallel computing easy and pervasive. HSA members are building a heterogeneous computing ecosystem, rooted in industry standards, which combines scalar processing on the CPU with parallel processing on kernel agents including GPU, DSP, and other accelerators. This enables high bandwidth access to memory and high application performance with low power consumption. HSA defines interfaces for parallel computation using CPU, GPU, DSP, FPGA and other programmable and fixed function devices, while supporting a diverse set of high-level programming languages, and creating the foundation for next-generation, general-purpose computing.
HSA Heterogeneous Computing
Based on heterogeneous computing technology, the heterogeneous multi-core processor deeply integrates CPU, GPU, DSP, FPGA, ASIC and other different types of processor cores and on the same chip for collaborative computing, storage and management in accordance with consistent hardware / software interface standards and specifications.
Goal of the Heterogeneous Computing
Compared with the prior homogeneous multicore processors and the same type of SoC chips, heterogeneous multi-core processors have significantly improved performance by up to orders of magnitude in terms of performance, power and other key indicators.